The present invention is related to semiconductor microelectronic circuit fabrication, and particularly to ion implantation using plasma immersion.
The formation of semiconductor junctions on the surface of a semiconductor crystal (such as silicon wafer) is generally carried out by implantation of ions of either acceptor or donor impurity species (e.g., Boron or Arsenic) into the surface. Currently, ion implantation is efficiently carried out by ion beam accelerators. An ion beam accelerator raster-scans a beam of donor or acceptor ions across the semiconductor wafer surface. The implanted semiconductor wafer surface is then annealed at elevated temperatures in excess of 600° C. in order to cause the implanted species to be substituted for silicon atoms within the crystal lattice. This process is defined as dopant activation. The depth of the implanted species below the surface, in conjunction with a subsequent anneal process, determines the junction depth, which is determined by the kinetic energy of the ion beam and subsequent annealing thermal budget. The conductance of the implanted region of the semiconductor is determined by the junction depth and the volume concentration of the thermally activated implanted dopant species. The implanted dopant species concentration is controlled by the rate at which the ion beam is scanned across the semiconductor surface and the beam current. The activated implanted dopant species concentration is controlled by the above, and the subsequent anneal process (temperature and time characteristics). For current semiconductor fabrication processes, in which semiconductor circuit feature size is about 130 nm, ion beam accelerators are suitable for ion implantation because the junction depth is fairly deep (over 330 Angstroms) and the required dopant dose is fairly modest (about 2×1014 to about 2×1015 ions/cm2). Such a modest dopant concentration is fulfilled by an ion beam accelerator with an implant operation lasting only minutes. Because of the deep junction depth, the abruptness of the junction need be no smaller than 6 nm/dec (i.e., nanometers per decade of concentration). Therefore, ion energy distribution is not critical, and some ions may have a kinetic energy that carries them somewhat beyond the desired junction depth without degrading the abruptness beyond the 4.1 nm/dec level. Therefore, techniques for enhancing the ion beam flux that compromise ion energy distribution can be used. These techniques include using an ion beam that has a few times the kinetic energy corresponding to the desired junction depth, or about 2 keV, (and therefore several times the ion flux density), and then electrically decelerating the ion beam down to the correct kinetic energy (e.g., 500 eV) just before it impacts the semiconductor wafer surface. The deceleration process is not precise and leaves a fraction of implanted particles (neutrals) above the correct energy level, which is sometimes referred to as a high energy tail or energy contamination. The high energy tail arises from the natural occurrence of neutrals in the ion beam and the immunity of such neutrals from the electrostatic deceleration process. Such neutrals therefore impact the wafer at the original energy (e.g., 2 keV), so that they are implanted below the desired junction depth, due to the high energy tail, causing a loss of junction abruptness. But this is not harmful because of the relatively relaxed requirement for junction abruptness (6 nm/dec). Moreover, rapid thermal annealing by halogen lamps, for example, tends to “wash out” the effect of the high energy tail due to diffusion.
However, as semiconductor circuit feature size decreases with progress in device speed, ion beam accelerators become less efficient. For example, at a feature size of 65 nm, the junction depth is only about 170 Angstroms and the abruptness is much steeper, at 2.8 nm/dec. With such a shallow junction, the required dopant dose is greater (to avoid an increased resistance), or about 1015 to about 2×10 ions/cm2. In order to activate such higher dopant concentrations in the silicon crystal, and in order to avoid increasing junction depth during annealing, dynamic surface annealing is advantageously employed, in which the wafer surface (e.g., down to depth of order 1000 Angstroms) is laser-heated to near melting (e.g., 1300 deg. C.) for a period of a nanosecond to tens of milliseconds. Dynamic surface annealing activates a higher concentration of dopant and increases junction depth by less than 20 Å compared with rapid thermal annealing. (By comparison, rapid thermal annealing can add over 100 Å to the junction depth, which would double the junction depth in some cases.) However, dynamic surface annealing does not reduce the high energy tail. Therefore, in order to stay within the more stringent junction abruptness requirement and in order to avoid a high energy tail, the ion beam accelerator must be operated in drift mode, in which the ions are accelerated up to but not beyond the kinetic energy corresponding to the desired junction depth (e.g., only 500 eV), so that no ions will be implanted below the desired depth, and no deceleration process is required. For example, a junction depth of 10-20 nm may translate to an ion beam energy of only 500 eV. Unfortunately, the lower ion energy in drift mode limits the ion beam flux (and current), so that the time required to reach the desired high dopant concentration can be as long as a half hour or one hour. This problem arises particularly in shallow junction implant of light species such as Boron, in which the beam voltage must be reduced to avoid high velocity Boron ions being implanted below the desired junction depth. The problem arises basically because the space charge effects in the ion beam produce repulsive forces between the ions in the beam in a radial direction, generally, limiting the beam density and therefore the beam current. Such effects become more important as the beam energy is reduced (as it must be for implanting the lighter elements such as Boron), resulting in lower beam currents and longer implant times. Such long implant times greatly limit productivity and increase production costs. For example, in order to avoid a decrease in wafer through-put, the number of ion beam implant machines must be increased. In the future, feature sizes will decrease further, down to 45 nm, so that such problems will worsen in proportion as the technology advances.
These problems pertain particularly to cases in which the species to be implanted has a low atomic weight (such as Boron), so that the acceleration voltage must be small, which translates into a small ion beam flux and a long implant time. For higher atomic weight species (such as Arsenic), the acceleration voltages are much higher and the ion beam flux is therefore sufficiently high to keep implantation times down to an acceptable level. One way of permitting an increased beam acceleration voltage for lighter implant species such as Boron, in order to improve ion flux and reduce implant time, is to implant molecular ions consisting of one Boron atom or more and another volatile species such as Fluorine, Hydrogen, or other species. Examples of such molecular ions are BF2, B10H14. Thus, implanting BF2 permits the use of a much higher beam energy and therefore a higher and more acceptable ion beam flux. However, while much of the implanted fluorine tends to diffuse out of the silicon crystal during annealing, a significant amount does not, leaving some crystal lattice sites that contain neither a semiconductor atom (Si) nor a dopant impurity atom (B), thus (for some applications) reducing the overall quality of the semiconductor material. Therefore, this technique is not desirable universally for all applications.
In summary, advances in technology dictate a more shallow junction depth, a greater junction abruptness and a higher dopant concentration in the semiconductor surface. Such advances in technology (where features size decreases to 65 nm and ultimately to 45 nm) render ion beam implantation of lighter dopants such as Boron impractical. This is because the traditional ion beam implanter provides too little ion beam flux in such applications.
In order to find an ion source having much higher ion flux for low atomic weight species such as Boron, the field has turned to an ion source whose flux at a given implant depth is less affected by the space charge effect or (indirectly) atomic weight, namely a plasma ion source. Specifically, the semiconductor wafer is immersed in a plasma consisting of dopant ions (such as Boron ions). However, such plasma ion immersion implantation has been plagued by various difficulties.
One type of plasma immersion ion implantation reactor employs a pulsed D.C. voltage applied to a pedestal supporting the semiconductor wafer in a vacuum chamber filled with a dopant-containing gas such as BF3. The D.C. voltage creates a plasma discharge in the chamber in which Boron ions and other ions dissociated from the BF3 ions are accelerated into the wafer surface. The D.C. voltage maintains the plasma by creation of secondary electrons from collisions with the chamber surfaces or wafer surface. The rate at which such collisions produce secondary electrons depends upon the condition of the chamber surfaces. Accordingly, such a reactor is unacceptably sensitive to changes in the condition of the chamber surfaces due, for example, to contamination of the chamber surfaces. As a result, such a plasma ion immersion implantation reactor cannot maintain a target junction depth or abruptness, for example, and is plagued by contamination problems.
This type of reactor tends to produce a relatively low density plasma and must be operated at relatively high chamber pressure in order to maintain the plasma density. The high chamber pressure and the lower plasma density dictate a thicker plasma sheath with more collisions in the sheath that spread out ion energy distribution. This spreading can result in a larger lateral junction distribution and may reduce junction abruptness. Furthermore, the reactor is sensitive to conditions on the wafer backside because the plasma discharge depends upon ohmic contact between the wafer backside and the wafer support pedestal.
One problem inherent with D.C. voltage applied to the wafer support is that its pulse width must be such that the dopant ions (e.g., Boron) are accelerated across the plasma sheath near the wafer surface with sufficient energy to reach the desired junction depth below the surface, while the pulse width must be limited to avoid (discharge) any charge build-up on the wafer surface that would cause device damage (charging damage). The limited pulse width is problematic in that the periodic decrease in ion energy can result in deposition on the semiconductor surface rather than implantation, the deposition accumulating in a new layer that can block implantation during the pulse on times. Another problem arises because ions must impact the wafer surface with at least a certain target energy in order to penetrate the surface up to a desirable depth (the as-implanted junction depth) and become substitutional below the surface and up to the desired annealed junction depth during the annealing process. Below this energy, they do not penetrate the surface up to the as-implanted junction depth and do not become substitutional at the desired junction depth upon annealing. Moreover, the ions below the target energy may simply be deposited on the wafer surface, rather than being implanted, to produce a film that can impede implantation. Unfortunately, due to resistive and capacitive charging effects (RC time constant) on dielectric films on the wafer that tend to accompany a D.C. discharge, the ions reach the target energy during only a fraction of each pulse period (e.g., during the first microsecond), so that there is an inherent inefficiency. Moreover, the resulting spread in ion energy reduces the abruptness of the P-N junction. This problem cannot be solved by simply increasing the bias voltage, since this would increase the junction depth beyond the desired junction depth.
Another type of plasma immersion ion implantation reactor employs inductive coupling to generate the plasma, in addition to the pulsed D.C. voltage on the wafer. This type of reactor reduces the problems associated with plasma maintenance from secondary electrons, but still suffers from the problems associated with pulsed D.C. voltages on the wafer discussed immediately above.
Another type of plasma ion immersion implantation reactor employs an RF voltage applied to the wafer support pedestal that both controls ion energy and maintains the plasma. As in the pulsed D.C. voltage discussed above, the RF voltage on the wafer support creates a plasma discharge in the chamber in which Boron ions and other ions dissociated from the BF3 ions are accelerated into the wafer surface. The RF voltage generates and maintains the plasma mainly by capacitively coupling RF energy from the electrode across the sheath to electrons in the plasma just above the sheath (low pressure case) or electrons in the bulk plasma volume (high pressure case). While such a reactor has reduced sensitivity to chamber surface conditions as compared to reactors employing a pulsed DC bias, it is still quite sensitive. Also, ion energy and flux cannot be independently selected with a single RF power source. Ion flux may still be unacceptably low for high throughput applications with a single RF power source. Contamination due to wall sputtering or etching may also be high due to elevated plasma potential.
Another type of plasma ion immersion implantation reactor employs a microwave power applicator for generating the plasma. This reactor has a microwave waveguide pointed axially downward to a magnetic field centered about the axis. Electron cyclotron resonance (ECR) occurs in a particular surface of the field to produce the plasma (for a microwave frequency of 2.45 GHz, this surface is where the magnetic field is about 875 gauss). The magnetic field is divergent, with a field gradient creating a drift current towards the substrate being processed. This drift current consists of both electrons (directly acted on by the interaction of microwave induced electric field and divergent DC magnetic field) and positively-charged ions (indirectly acted on by the deficit in negative charge formed due to the out-flux of electrons) and corresponding to a voltage of 10 to 100 eV. One problem is that the magnetic field gradient is non-uniform, so that the radial distribution of plasma ion energy is non-uniform, causing non-uniform junction depths across the wafer. Another problem is the relatively high ion energy directed at the wafer, limiting the degree to which junction depths can be minimized. One way of addressing the non-uniformity issue is to place the microwave ECR source far above the wafer. The problem with such an approach is that the ion density and flux is at least proportionately decreased, thus reducing the productivity of the reactor. A related problem is that, because the plasma ion density at the wafer surface is reduced by the increased source-to-wafer distance, the chamber pressure must be reduced in order to reduce recombination losses. This rules out some applications that would be advantageously carried out at high pressure (applications which benefit from wide angular ion energy distribution) such as conformal doping of polysilicon lines and three dimensional devices. Another way of addressing the non-uniformity issue is to place another magnet array between the source and the wafer, in an effort to straighten the magnetic field. However, the additional magnetic field would increase magnetic flux at the wafer surface, increasing the risk of charge damage to semiconductor structures on the wafer.
In summary, plasma immersion ion implantation reactors have various limitations, depending upon the type of reactor: plasma reactors in which a pulsed D.C. voltage is applied to the wafer pedestal are too sensitive to chamber conditions and are inefficient; and plasma reactors with microwave ECR sources tend to produce non-uniform results. Thus, there is a need for a plasma immersion ion implantation reactor that is free of the foregoing limitations.